Increasing the parallelism of a turbo decoder significantly constrains the inherently recursive decoding algorithm and limits its ability to efficiently achieve high decoding throughputs and to lower latency. This is partly due to the interleavers that impose precedence constraints when exchanging extrinsic information between the constituent decoders. In this paper, we introduce the notion of a generalized decoding schedule, which enables to configure the order in which decoder metrics and extrinsic information are exchanged during the decoding process. This schedule is generally inferred from the choices related to the hardware architecture and its parallelism degree. By following the proposed framework, it is possible to evaluate the achieved latency of any decoding schedule at a given operating point. We then propose a novel iteration overlap decoding schedule that can strike an excellent performance/latency tradeoff: Corresponding simulation results show that latency can be reduced by half for high rate LTE decoders for a given error rate target.