Drain Current Variability in 2-levels Stacked Nanowire Gate All Around P-type Field Effect Transistors - CMNE
Conference Papers Year : 2023

Drain Current Variability in 2-levels Stacked Nanowire Gate All Around P-type Field Effect Transistors

Abstract

An experimental study of drain current statistical characteristics in two vertically stacked nanowire MOSFETs (bottom one: Omega shaped and top one: nanowire) is presented. The most critical parameter variations are identified using an advanced mismatch model that well describes the experimental results, while the impact of channel geometry is examined for every source of process variations.
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Dates and versions

hal-04305370 , version 1 (27-11-2023)

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Donghyun Kim, Sylvain Barraud, Gérard Ghibaudo, Christoforos Theodorou, Jae Woo Lee. Drain Current Variability in 2-levels Stacked Nanowire Gate All Around P-type Field Effect Transistors. 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Mar 2023, Seoul, South Korea. pp.1-3, ⟨10.1109/EDTM55494.2023.10103067⟩. ⟨hal-04305370⟩
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